Cache Pipelining with Partial Operand Knowledge

Caches consume a significant amount of power in modern microprocessors while also constraining clock frequency due to their access time. In this paper, we propose a bit-sliced cache, which reduces dynamic power consumption and achieves higher clock frequency as well as increased cache throughput while adding little complexity. Our bit-sliced cache reduces 20-40% of dynamic power for a variety of cache organizations by activating only the necessary row decoders and subarrays. To reduce cycle time, the cache access is pipelined, which results in higher bandwidth without suffering from the complexity and power and area penalty caused by an additional cache port. We report cycle time improvements nearly proportional to the degree of bit-slice pipelining, as well as performance improvements averaging 9% and 11% for an out-of-order processor with a 2-sliced and 4-sliced cache and ALU.